implement unsigned operators

This commit is contained in:
2021-11-11 23:04:41 +01:00
parent d3e882cba0
commit 51cf8a8d28
7 changed files with 161 additions and 51 deletions

View File

@@ -413,43 +413,58 @@ fn emit_expression<'a>(ctx: &mut FunctionContext<'a>, expr: &'a ast::Expression)
(I32, Sub) => Instruction::I32Sub,
(I32, Mul) => Instruction::I32Mul,
(I32, Div) => Instruction::I32DivS,
(I32, DivU) => Instruction::I32DivU,
(I32, Rem) => Instruction::I32RemS,
(I32, RemU) => Instruction::I32RemU,
(I32, And) => Instruction::I32And,
(I32, Or) => Instruction::I32Or,
(I32, Xor) => Instruction::I32Xor,
(I32, Eq) => Instruction::I32Eq,
(I32, Ne) => Instruction::I32Neq,
(I32, Lt) => Instruction::I32LtS,
(I32, LtU) => Instruction::I32LtU,
(I32, Le) => Instruction::I32LeS,
(I32, LeU) => Instruction::I32LeU,
(I32, Gt) => Instruction::I32GtS,
(I32, GtU) => Instruction::I32GtU,
(I32, Ge) => Instruction::I32GeS,
(I32, Lsl) => Instruction::I32Shl,
(I32, Lsr) => Instruction::I32ShrU,
(I32, Asr) => Instruction::I32ShrS,
(I32, GeU) => Instruction::I32GeU,
(I32, Shl) => Instruction::I32Shl,
(I32, ShrU) => Instruction::I32ShrU,
(I32, ShrS) => Instruction::I32ShrS,
(I64, Add) => Instruction::I64Add,
(I64, Sub) => Instruction::I64Sub,
(I64, Mul) => Instruction::I64Mul,
(I64, Div) => Instruction::I64DivS,
(I64, DivU) => Instruction::I64DivU,
(I64, Rem) => Instruction::I64RemS,
(I64, RemU) => Instruction::I64RemU,
(I64, And) => Instruction::I64And,
(I64, Or) => Instruction::I64Or,
(I64, Xor) => Instruction::I64Xor,
(I64, Eq) => Instruction::I64Eq,
(I64, Ne) => Instruction::I64Neq,
(I64, Lt) => Instruction::I64LtS,
(I64, LtU) => Instruction::I64LtU,
(I64, Le) => Instruction::I64LeS,
(I64, LeU) => Instruction::I64LeU,
(I64, Gt) => Instruction::I64GtS,
(I64, GtU) => Instruction::I64GtU,
(I64, Ge) => Instruction::I64GeS,
(I64, Lsl) => Instruction::I64Shl,
(I64, Lsr) => Instruction::I64ShrU,
(I64, Asr) => Instruction::I64ShrS,
(I64, GeU) => Instruction::I64GeU,
(I64, Shl) => Instruction::I64Shl,
(I64, ShrU) => Instruction::I64ShrU,
(I64, ShrS) => Instruction::I64ShrS,
(F32, Add) => Instruction::F32Add,
(F32, Sub) => Instruction::F32Sub,
(F32, Mul) => Instruction::F32Mul,
(F32, Div) => Instruction::F32Div,
(F32, Rem | And | Or | Xor | Lsl | Lsr | Asr) => unreachable!(),
(
F32,
DivU | Rem | RemU | And | Or | Xor | Shl | ShrU | ShrS | LtU | LeU | GtU | GeU,
) => unreachable!(),
(F32, Eq) => Instruction::F32Eq,
(F32, Ne) => Instruction::F32Neq,
(F32, Lt) => Instruction::F32Lt,
@@ -461,7 +476,10 @@ fn emit_expression<'a>(ctx: &mut FunctionContext<'a>, expr: &'a ast::Expression)
(F64, Sub) => Instruction::F64Sub,
(F64, Mul) => Instruction::F64Mul,
(F64, Div) => Instruction::F64Div,
(F64, Rem | And | Or | Xor | Lsl | Lsr | Asr) => unreachable!(),
(
F64,
DivU | Rem | RemU | And | Or | Xor | Shl | ShrU | ShrS | LtU | LeU | GtU | GeU,
) => unreachable!(),
(F64, Eq) => Instruction::F64Eq,
(F64, Ne) => Instruction::F64Neq,
(F64, Lt) => Instruction::F64Lt,